Solved bca assignment

a) Difference between Latch and flip flop

Latches are Level Sensitive, while Flip-Flops are Edge  Sensitive.
A positive level latch is transparent to the positive level(enable), and it lathes the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.
A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negedge flop) only.
For posedge flop check out the Morris mano book (digital design), in that he gave how the flop behaves with respect to an edge. (Explained with Gate level logic diagram). This will gives you a clear picture of Flop.

The main difference between latches and flip-flops is the method used to change their states. Latches are level sensitive, or level-triggered. This means that the outputs are dependent on the voltage level applied, not on any signal transition. Flip-flops are edge-triggered, that is that they depend on the transition of a signal. This may either be a LOW-to-HIGH (rising edge) or a HIGH-to-LOW (falling edge) transition.

b) Synchronous and Asynchronous latches:

A  asynchronous/synchronous  latch circuit that includes a first, second, and third latch element, an asynchronous latch section, and a clock control section. When operated as a synchronous latch, the first latch element operates as the "master" portion and the second latch element acts as the "slave" portion of a master/slave latch. The clock control circuit enables the clock signals to control the synchronous operation of the master/slave latch. When operated as an asynchronous latch, the clock control circuit disables the clock. The output of the asynchronous latch section is connected to the input of the first latch element. An asynchronous signal appearing on one of the inputs of the asynchronous latch section passes through the first and second latch elements and is applied to another input of the asynchronous latch section, causing it to be latched, or held. Separate outputs are provided for the asynchronous latch and the synchronous latch. When scanning occurs, the second and third latch elements act as a shift register stage. The second latch element acts as the master while the third latch element acts and the slave of a master/slave latch. The contents of the asynchronous latch can be latched in the slave section of the synchronous latch for scanning. Shift-in data is coupled to the master, then transferred to the slave, where it appears on the shift-out output, by appropriate clock signals.